Arrangement for preventing the locking of wheels of motor vehicles

ABSTRACT

A D.C. voltage of amplitude inversely proportional to vehicle speed is directly applied to the second inputs of a first and second comparator stage. The D.C. voltage is also applied to a logarithmic circuit and then differentiated. The output of the differentiator is applied to the first input of the second comparator stage and further, through an inverter, to the first input of the first comparator stage. The outputs of the comparator stages control, through a switching amplifier, the operation of an electrically operated pressure decreasing brake valve.

United States Patent 1 Runge et al.

ARRANGEMENT FOR PREVENTING THE LOCKING OF WHEELS OF MOTOR VEHICLESInventors: Detlev Runge, Gerlingen; Werner Giitz, Monsheim, both ofGermany Assignee: Robert Bosch GmbH, Stuttgart, Germany Filed: Dec. 21,1971 Appl. No.: 210,400

Foreign Application Priority Data Dec. 28, 1970 Germany ..P 20 64 067.9

ms. Cl ..307/10 R, 303/21 co Int. Cl. ..B60t 8/10 Field of Search..307/10 R; 303/21 R,

303/21 P, 21 BE,21 CG; 188/181 A; 317/5; 340/262; 324/162 PrimaryExaminer-Herman J. Hohauser Assistant ExaminerM. GinsburgAttorney-Michael S. Striker [57] ABSTRACT A DC. voltage of amplitudeinversely proportional to vehicle speed is directly applied to thesecond inputs of a first and second comparator stage. The DC. voltage isalso applied to a logarithmic circuit and then differentiated. Theoutput of the differentiator is applied to the first input of the secondcomparator stage and further, through an inverter, to the first input ofthe first comparator stage. The outputs of the comparator stagescontrol, through a switching amplifier, the operation of an electricallyoperated pressure decreasing brake valve.

27 Claims, 12 Drawing Figures 5/ 53 5 (6 {g 9 llllll-+- 0/? b0?-Pqtenttd May 29, 1973 3,736,435

6 Shoots-Shoot 1 Patented May 29, 1973 3,736,435

5 Shoots-Shoot z f/rev-ifrop/vsy Patented May 29, 1973 5 Shuts-Shoot 3i; ILIIII l. I :21 .liailll illivlll||llLl i Q mw //vr,swr0P5 55/! Puma;Werner G'TZ 3/ Patented May 29, 1973 5 Sheets-Shoot 4 f/IQrArm /WYPatented May 29, 1973 3,736,435

5 Sheets-Shoat 5 .Je/Ier Pwva; h erner fly BACKGROUND OF THE INVENTIONThis invention relates to a control arrangement for preventing thelocking of a at least one wheel of a motor vehicle. In particular, itrelates to such control arrangements wherein a D.C. voltage dependentupon the speed of rotation of the wheel is generated and, therebyfurnishing an acceleration signal. Further, in these known systems acomparator circuit is furnished which operates a valve decreasing thebrake pressure in dependence upon the amplitude of the abovementionedacceleration signal.

In a known arrangement of the above-described type, the D.C. voltage isderived from a pulse generator which furnishes a pulse sequence having arepetition rate porportional to the rotational speed of the wheel andhaving a converter circuit whichfurnishes this D.C. voltage as afunction of the above-mentioned pulse sequence. The converter circuitmay for example be a low pass filter. The low pass filter forms a D.C.voltage whose amplitude is proportional to the rotational speed of thewheel.

The low pass filter must be so designed that even at low rotationalspeeds of the wheel its ripple voltage is not excessive. This is becauseexcessive ripple causes the differentiating circuit to respond toindividual waves of the ripple voltage. Thus as a rule the low passfilters must have a very steep cutoff with a top frequency lyingsomewhere between and 30 Hz.

The use of such a low pass filter results in a definite disadvantage inthat changes in the input frequency result in a change of output voltageafter a definite delay time only. Depending upon the cutoff frequency ofthe filter the delay time may be anywhere between 30 to 60 milliseconds.However, the control frequency of the overall circuitry is approximately10 Hz, so that the pressure decreasing valve is opened and closed oncewithin each 100 milliseconds. If the above-mentioned delay time isassumed to be 30 milliseconds, the brake pressure control circuit thusalways operates at a delay of a third of the period following the actualchanges in acceleration of the wheel. A control of the braking power onthe basis of optimum slippage is therefore difficult to achieve.

SUMMARY OF THE INVENTION It is an object of the present invention tofurnish a control circuit for valves operating to prevent the locking ofa wheel of a motor vehicle, said control circuit having a substantiallysmaller delay time than the delay time of conventional circuits of thistype.

In accordance with this invention, a D.C. output voltage is furnishedwhich is inversely proportional to the speed of the motor vehicle. ThisD.C. voltage is applied to the input of second circuit means whichfurnish a second signal having an amplitude varying as a logarithmicfunction of the D.C. voltage. Differentiation means are connected tosaid second circuit means for differentiating said second signal,thereby furnishing an acceleration signal. Comparator means compare saidacceleration signal and said D.C. voltage and furnish a comparatoroutput signal which, in turn, operates brake control means. In apreferred embodiment of the present invention the brake control meanscomprise electrically operative valve means which decrease the pressurein the brake line.

The novel features which are considered as characteristic for theinvention are set forth in particular in the appended claims. Theinvention itself, however, both as to its construction and its method ofoperation, together with additional objects and advantages thereof, willbe best understood from the following description of specificembodiments when read in con nection with the accompanying drawing.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a block diagram of a firstembodiment of the present invention;

FIG. 2 is a block diagram of a second embodiment of the presentinvention;

FIG. 2a is a variation of the embodiment shown in FIGS. 1 and 2;.

FIG. 3 is a circuit diagram of the essential blocks of the system shownin FIG. 1;

FIG. 3a is a circuit diagram corresponding to the block diagram of FIG.2a;

FIG. 3b is a part of the circuit diagram corresponding to the blockdiagram of FIG. 2;

FIG. 4 is a block diagram of a safety arrangement usable in conjunctionwith the systems of FIGS. 1 and 2;

FIG. 5 is a circuit diagram of the safety arrangement shown in FIG. 4;

FIG. 6 is a sketch of a pulse generator;

FIG. 7 is a diagram showing the braking power as a function of slippage;

FIG. 8 is a diagram useful in explaining the operation of the system ofFIG. 1; and

FIG. '9 is a diagram for explaining the operation of the system of FIG.2.

DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of thepresent invention will now be described with reference to the drawing.

Referring first to FIG. 1, reference numeral 11 denotes a pulsegenerator which is connected with the wheel of the vehicle and furnishesan A.C. voltage with frequencies proportional to the speed of saidwheel. The output of this pulse generator is connected to a monostablecircuit, 12, whose output is in turn connected to a sawtooth generator13 followed by a peak rectifier 15. The above-mentioned circuitsconstitute first circuit means. Second circuit means comprise alogarithmic stage 16 whose input is connected to the output of the peakrectifier and whose output is connected to a band pass filter 17. Theoutput of band pass filter 17 is connected to differentiation circuitmeans, 19. Further shown in FIG. 1 are comparator means comprising afirst comparator stage 21 and a second comparator stage 22. The outputof peak rectifier 15 is directly connected to the second inputs of thefirst and second comparator stage. The output of the differentiationmeans is directly connected to the first input of the second comparatorstage and, via an inverter 20, to the first input of the firstcomparator stage 21. The outputs of comparator stages 21 and 22 areconnected to the inputs of first storage means 23. The output of firststorage means 23 operates a pressure reducing valve 25 through aswitching amplifier 24. The pressure reducing valve 25 is connected intothe brake line 26.

The second embodiment of the invention, shown in block diagram form inFIG. 2 differs from the abovedescribed block diagram only in thatcomparator stage 21 is replaced by a comparator stage 210 whose secondinput is grounded and whose first input is connected to the output ofthe differentiation circuit means 19 not only through inverter 20 butalso through additional differentiation means 27.

In FIG. 2a an alternate embodiment for the first circuit means of FIGS.1 and 2 is shown. Here peak rectifier is replaced by a sample and holdcircuit 60. Sample and hold circuit 60 has a first and second input, thefirst input being connected to the output of sawtooth generator 13,while the second input is connected to a second output of monostablecircuit 12.

FIG. 3 shows a circuit diagram of blocks 12 to 22 of FIG 1. Monostablecircuit 12 comprises transistors 120 and 121 both of whose emitters areconnected to the negative supply line 40. The collectors of the twotransistors are connected to the positive supply line 41 via resistors122 and 123 respectively. The collector of transistor 120 is connectedthrough a resistance 124 to the base of transistor 121, and a capacitor126 is connected in parallel with resistance 124. The collector oftransistor 121 is connected to the base of transistor 120 through acapacitance 125. The base of resistance 120 is further connected to thepositive supply line 41 through a resistance 127 and to a terminal 129through a diode 128. Capacitor 126 serves to furnish steep pulse edges.Terminal 129 is connected to the output of pulse generator 11.

Sawtooth generator 13 comprises a storage capacitor 138, herein referredto as the first storage capacitor. This capacitor is slowly charged inthe interval between two output pulses of the monostable circuit 12through a constant current source comprising a transistor 130. Thecollector of transistor 130 is connected to capacitor 138 through adiode 137, while its emitter is connected to the collector of transistor121 through a resistance 131. Transistor 130 is a pnp transistor whosebase is connected to the tap of a variable resistance 135 which formspart of a voltage divider connected between the collector of transistor121 and line 40. The voltage divider comprises a diode 133 having ananode connected to the collector of transistor 121 and a cathodeconnected to the anode of diode 134 whose cathode is in turn connectedto one terminal of the abovementioned variable resistance 135. The otherterminal of variable resistance 135 is connected through a furtherresistance 136 to the minus line 40. Diodes 133 and 134 serve astemperature compensation of the temperature varying emitter-base diodeof pnp transistor 130.

Storage capacitor 138 is discharged through a first switching transistor140. Specifically, one terminal of capacitor 138 is connected to thecollector of npn transistor 140, whose emitter is connected to thepositive supply line 41 through a resistance 142 and to the negativesupply line through a resistance 141. The base of transistor 140 isconnected through a capacitance 143 to the collector of transistor 120and through a resistance 144 to negative supply line 40.

The voltage across capacitor 138 is applied through a resistance 153 tothe base of a transistor 150 which forms part of peak rectifier l5.Transistor 150 serves as an impedance changing stage and is connected asan emitter follower. A resistance 152 connects the emitter of transistorto the negative line 40, while its collector is directly connected toline 41. The voltage across emitter resistance 152 is applied to asecond storage capacitor 155 through a diode (first diode means) 154.The discharge of capacitor 155 takes place through a constant currentsource comprising a transistor 151 having an emitter resistance 156,whose base voltage is derived from a voltage divider comprisingresistors 158 and 157. The circuit is so designed that the dischargecurrent from capacitor 155 is considerably less than the chargingcurrent thereto. For example the discharge current may be adjusted to avalue corresponding to a vehicle deceleration of 100 n/sec. Transistor151 and its associated circuitry are herein referred to as secondconstant current source means.

The voltage across capacitor 155 is applied to the base of a transistor160 through a resistance 162. Transistor 160 forms part of the secondcircuit means. It is a logarithmic stage whose input, namely transistor160 is again an emitter-follower stage having an emitter resistance 161.Connected in parallel with resistance 161 is the series combination of aresistance 163 and a diode 164. The cathode of diode 164 is connected tothe negative line 140. I

The voltage appearing across diode 164 is applied to band pass amplifiermeans 17 through resistance 165. The band pass amplifier 17 comprisestwo stage amplification having transistors and 171. First transistor 170has an emitter resistance 172 and a collector resistance 177, while thesecond transistor 171 has an emitter resistance 178 and a collectordirectly connected to the positive line 41. The collector of transistor170 is connected to the base of transistor 171 through a resistance 176.Feedback and shunting elements are provided to eliminate both high andlow frequencies.

A capacitor 174 connected in parallel with emitterresistance 172 allowsnegative feedback at low frequencies. For the suppression of highfrequencies a double T element is furnished which is connected betweenthe emitter of transistor 171 and the base of transistor 170. Thisdouble T element consists of two resistances, 181, 184 and threecapacitors, 183, 182, 175. High frequencies are also shunted bycapacitor 173 connected in parallel with collector resistance 177.

Connected in cascade with band pass amplifier 17 are differentiationmeans 19. The active element therein is an operational amplifier 190.The voltage at the emitter of transistor 171 is fed to the invertinginput of operational amplifier through a resistance 194 and adifferentiating capacitor 195. The voltage at the direct input ofoperational amplifier 190 is derived from a voltage divider havingresistors 192 and 193 through a resistance 191 connected between thevoltage divider tap and the direct input of operational amplifier 190.The output of operational amplifier 190 is coupled to the invertinginput through a resistance 196 in parallel with a capacitor 197.Resistance 194 and capacitor 197 serve to suppress high frequencyvoltage spikes.

The second comparator stage 22 comprise an operational amplifier 220which has no feedback and whose inverting input receives the outputvoltage of differentiation means 19 via a capacitor 198 and an inputresistance 224. The output voltage of peak rectifier 15 is applied tothe direct input of operational amplifier 220 through a voltage dividerhaving resistors 222 and 223, via an input resistance 221. It will benoted that the output voltage of the peak rectifier is derived from theemitter of transistor 160 and is applied to the voltage divider havingresistors 222 and 223 through a line 43. A resistance 226 connects thecommon point of capacitor 198 and resistance 224 to minus line 40.

The first comparator stage 21 is similarly connected as secondcomparator stage 22 and has an operational amplifier 210. An inverterstage 20 is connected between the output of differentiating means 19 andthe inverting input of operational amplifier 210. Inverter stage 20 hasa transistor 200 having a collector resistance 202 and an emitterresistance 201. The base of transistor 200 is connected with the commonpoint of two resistances 203 and 204 which, together with a thirdresistance 205 form a voltage divider. The output of differentiatingmeans 19 is connected via a capacitor 199 to the common point ofresistances 204 and 205. The output of operational amplifier 210 isconnected with an output terminal 215, while the output of operationalamplifier 220 is connected to an output terminal 225. Both of theseoutput terminals are connected to i the inputs of a storage stage 23, asreference to FIG. 5

will show. Storage stage 23 constitutes first storage means.

FIG. 3a shows the circuit of sample and hold circuit 60. A transistor601 connected as an emitter follower and having an input resistance 606and an emitterresistance 607 constitutes the input to the stage. Theoutput of the stage is an impedance changing stage, namely a Darlingtoncircuit comprising transistor 604 and 605. Power output transistor 605has an emitter resistance 613, while preamplifier transistor 604 has abase resistance 612. The emitter of transistor 605 is connected to aninput terminal 617 which is connected to the input of the second circuitmeans, that is logarithmic stage 16 or, more specifically, resistance162 of said stage. Similarly, input terminal 614 connected to resistance606 in FIG. 3a is connected to the output of sawtooth generator 13, thatis the collector of transistor 140.

Connected to the emitter of input transistor 601 is the collector of atransistor 602 whose emitter is connected to the collector of a secondtransistor 603. The emitters of both transistors 602 and 603 areconnected to minus line 40 through a capacitor, 609 and 611respectively. Base resistance 612 is connected to the emitter oftransistor 603. The base of transistor 602 is connected to an inputterminal 615 via a resistance 608, while the base of transistor 603 isconnected to an input terminal 616 via a resistance 610. Input terminal615 and 616 may be connected to the two outputs of monostablemultivibrator 12, that is with the collectors of transistors 120 and 121respectively.

FIG. 3b shows a circuit which may be substituted for the additionaldifferentiating means 27 of FIG. 2. The direct and inverting input ofoperational amplifier 210a are connected to the output of inverter 20through a resistance 211 and 214 respectively. They are furtherconnected via a resistance 217 and 216 to the common point of resistors212 and 213 which form a voltage divider. The non-inverting input isfurther connected to ground via capacitor 218.

FIG. 5 shows a safety arrangement which closes pressure decreasing valve25 for an adjustable time interval in case the control circuit begins tooscillate. The output of storage means 23 is connected to its inputthrough monostable feedback circuit means 28. Further, the output ofstorage stage 23 is connected to the input of a switching amplifier 24,to the first input of a third comparator stage 32 and to the input of athird monostable stage 30. The output of monostable stage 30 isconnected to the second input of the third comparator stage 32. Theoutput of third comparator stage 32 controls the base of a switchingtransistor 350 via a fourth monostable circuit 33. The emitter oftransistor 350 is connected to ground, while its collector is connectedwith the input of switching amplifier 24.

Reference to FIG. 5 shows that storage stage 23, the first storagemeans, comprise a bistable stage having transistors 230 and 231.Transistors 230, 231 have collector resistances 232, 233 respectively.The collector of each transistor is connected to the base of the othertransistor through a resistance 234, 235. A resistance 236 connects aninput terminal 215 to the collector of transistor 230 while a diode 238connects this terminal to the base of said transistor. Similarly, inputterminal 225 is connected to the base of transistor 231 through diode239 and to its collector through resistance 237.

The third monostable multivibrator 30 comprises a differentiating inputcomprising a capacitor 311, a resistance 312 and a diode 308.Transistors 300 and 301 respectively have collector resistances 302 and303. The collector of transistor 300 is capacitively coupled through acapacitor 304 to the base of the second transistor 301, while thecollector of transistor 301 is connected to the base of transistor 300via a resistance 305. The base of transistor 301 is further connected topositive line 41 via a resistance 306.

Third comparator stage 32 comprises an operational amplifier 320 whichhas no feedback, but has two input resistances 321 and 322.

Fourth monostable stage 33 is similarly constructed to third monostablestage 30 and differs from said third stage only in the components used.Reference numbers of the individual elements are increased by 30relative to the third monostable stage 30. I

Switching amplifier 24 comprises a power transistor 240 which has a baseresistance 241. The base is also connected with the collector ofswitching transistor 350. The base of switching transistor 350 isconnected to the output of the fourth monostable stage 33 via aresistance 351. The activating winding 251 of the pressure decreasingvalve 25 is connected between the collector of transistor 240 andpositive line 41.

FIG. 6 is a sketch of pulse generating means 11. It comprises a toothedwheel 1 10 which is made from soft magnetic material and directlymounted on the shaft of the wheel of the vehicle. The wheel has teeth111 which are spaced one from the other by an angular distance of Ad)Mounted in operative proximity of the teeth is a horse-shoe shaped yoke112 which also is made of soft magnetic material and has a magnetizationcoil 1 13. At the terminal of this coil AC. voltage pulses of sinusoidalform are furnished when yoke 112is premagnetized by a DC. currentthrough coil 113.

FIGS. 7, 8 and 9 are going to be described in conjunction with thefunctional description of the circuit which now follows.

It has already been stated that it is a characteristic of the presentinvention that the first circuit means furnish an output voltage whichis inversely proportional to the speed of the vehicle, that is inverselyproportional to the repetition rate of the pulses furnished by pulsegenerator 11. Further, it is essential for the present invention that alogarithmic stage is included in the second circuit means which areinterconnected between the differentiation circuit means 19 and theoutput of the first circuit means.

Derivatives with respect to time are hereinafter designated by a dot:

E (M /d b E bl The rotational velocity of the wheel is the firstderivative of angle (1) or, as a good approximation, as the differentialIf it is assumed that the angular difference Ad) is equal to theconstant distance between teeth of the pulse generator (FIG. 6), namelyA then the time difference At is identical to the changing intervalbetween pulses 1'. Then the wheel velocity .1;-= A/ (61 Bydifferentiating equation (61) with respect to time the wheelacceleration is found to be:

5 A we) Equation (62) is not readily solved electronically. Therefore itwill be multiplied by r:

Here lnr is the natural logarithm of 'r. When the wheel begins to lock,the deceleration exceeds an upper limiting value at which the pressuredecreasing value 25 must be opened. Following this opening the wheelaccelerates again and, when a positive acceleration s is exceeded, thevalve must again be opened.

The two equations:

are solved by the circuit of FIG. 3 in an electronic manner.specifically, equation (63a) is solved by the second comparator stage 22while equation (63b) is solved by the first comparator stage 21. Inmonostable stage 12, under quiescent conditions first transistor 120 isconductive, while second transistor 121 is blocked. This means thatunder quiescent conditions the collector of the second transistor 121 issubstantially at the potential of positive line 141. When a negativepulse is applied from the pulse generator 11 to input terminal 129, thecollector potential of the second transistor 121 jumps to substantiallythe negative potential of line 40 for the duration of the pulse.Constant current source 130 in the sawtooth generator 13 thus chargesstorage capacitor 138 in the time between output pulses of monostablestage 12. Capacitor 138 is charged more, the longer the interval betweenoutput pulses of monostable stage 12. The length of this interval isapproximately equal to the interval between pulses 1' when the pulsewidth of the monostable stage 12 is sufficiently small. During the timethat an output pulse is furnished by monostable stage 12, storagecapacitor 138 is discharged through first switching transistor 140.

The output voltage of sawtooth generator 13 is connected to the input ofpeak rectifier l5. Capacitor the second storage capacitor is charged toa voltage which is proportional to the peak voltage of the sawtoothpulses and therefore proportional to the interval between pulses, 'r.The voltage atthe emitter of transistor is therefore proportional to thetime 1 between pulses and therefore inversely proportional to therotational wheel velocity (1). I

The sample and hold circuit 60 according to FIG. 2a serves the samefunction as peak rectifier 15, but furnishes an output voltage which hasless ripple. Transistors 601 and 602 (FIG. 3a) are conductive betweentwo output pulses of monostable stage 12. Thus the first capacitor 609is charged to a voltage which is proportional to the distance 1' betweenpulses. However, within the pulse duration of pulses furnished bymonostable stage 12, transistor 601 and 602 are blocked, whiletransistor 603 is conductive. During this time the second capacitor 611whose capacity is substantially less than that of first capacitor 609,is charged to the voltage existing on capacitor 609. The voltage acrosscapacitor 611 thus corresponds with very little delay and a very smallripple to the peak voltage furnished by sawtooth generator 13.

Equation (63a) and (63b) are thus solvable electronically. The constantthreshold values 4),, and d), are adjusted by means of voltage dividers23, 22 and 213, 212 respectively and multiplied withD.C. voltage 1' vialine 43. The voltages which correspond to the second side of the twoequations (63a) and (63b) are applied to the two second inputs ofcomparator stages 21 and 22 respectively. The negative sign in equation(63b) is taken into consideration by the inverter stage 20. The tworight-hand sides of equation (63a) and (63b) are identical and thecorresponding DC. voltage is derived from differentiation circuit 19.

The logarithmic element in the logarithmic stage 16 is a semi-conductordiode 164. Both germanium and silicon diodes have a logarithmiccharacteristic as at least part of their overall characteristic. Forsmall voltages in the conductive direction, the diodes first do notconduct at all. Above a threshold voltage (0.7 volts for silicon diodes)the current increases exponentially as a function of increasing voltage.This means that the voltage across the diode will vary logarithmicallywith current through the diode.

FIG. 8 shows the variation with respect to time of a regulating processusing the present invention. Solid curve 50 shows the variation ofvoltage derivative with respect to time (d/dt) lnr). Line 51 shows thevariation of input voltage rd), of second comparator stage 22,whiledashed line 52 shows the variation of input voltage rd), of firstcomparator stage 21.

When the arrangement for preventing the locking of the wheel of avehicle according to the present invention begins to operate, a brakingprocess takes place exactly as when known arrangements of this type areused. After the brake pedal is first activated, the decelerationincreases according to curve 50 until the first point designated with Ois reached. At this point Ad; (d/dt) (Mr) is equal to the adjustedthreshold value nil The second comparator stage 22 thus operates andopens the pressure reducing valve 25 so that the deceleration decreasesand a positive acceleration is applied to the wheel. This continuesuntil the first point designated with a S is reached. Here the firstcomparator stage 21 furnishes an output, closing the pressure decreasingvalve. This process repeats periodically until the vehicle stops at time13,.

The preferred embodiment of the present invention described up to thispoint constitutes an arrangement for preventing the locking the wheelsof a vehicle which operates considerably faster than known arrangementsof this type. There is no low pass filter and the peak rectifier has adelay time of less than 0.1 milliseconds. Band pass amplifier 17 ispreferably so designed that its amplification drops 3 dB at a lowerlimiting frequency of 7 Hz and at an upper frequency of 35 Hz. Thisamplifier then has a delay time of 3 milliseconds and successfullysuppresses small variations in amplitude and frequency of the outputpulses of pulse generator 11, such as may arise when holes in the roadare encountered.

Since differentiating means 19 have only a very small delay time ofapproximately 0.5 milliseconds, the total delay of the circuit accordingto FIG. 1 is smaller by a factor of IO than the delay factor of knowncircuit arrangements of this type.

When a sample and hold circuit 60 is used the delay time may bedecreased even further, since band pass amplifier 17 is no longeressential. The delay time of 3 milliseconds is thus eliminated and thedelay of sample and hold circuit 60 in itself is smaller than that ofpeak rectifier 15. The second embodiment of FIG. 2 further results inthe elimination of an additional difficulty. The plot in FIG. 7 of brakepower versus slippage shows that an operating point A should preferablybe reached at which the braking power is maximum. Since in the knowncontrol circuits andfor the first embodiment of the present inventiononly the wheel acceleration is measured, it is possible that undercertain road conditions only an operating point B is achieved which doesnot coincide with the maximum brake power. This is the case because onvery slippery streets the wheel tends to lock rapidly and comepractically to a standstill, that is, a condition of approximately 80percent slippage is reached. Then the pressure decreasing valve is openand the wheel is again positively accelerated. The adjusted thresholdvalue for closing of the pressure decreasing valve may then already bereached at, for example, 50 percent slippage (B). However, at operatingpoint B the lateral guidance of the wheel is considerably worse than atoperating point A, so that the vehicle will tend to skid. When operatingpoint A is to be exactly achieved, one must wait until the brake powerand thus the positive wheel acceleration reaches its maximum value A.The maximum ofdi is reached when the third derivative with respect totime of the angle of rotation, or the second derivative with respect totime of the angular speed, is equal to zero.

The following mathematical considerations explain with what circuits thevalue of may be determined.

Further differentiation of the equation labeled 62 results in thefollowing equation:

The element r'l'r is derived by differentiation of 'i/r with respect totime:

When equation (65) is substituted in the equation (64), the followingexpression for 4; results:

The second member derivative with respect to time (d/dt) (171) may bederived electronically from the output of the first differentiatingcircuit 19 by means of a second differentiating circuit 27.

The first member, ('i/r in equation (66) is, however, not readilyderived. However, in practical experiments, it has been found that thedelay time of the complete control arrangement may be compensated forwith sufficient accuracy if the element containing ('H'r) as well as thefactor of 1/7 before the square brackets in equation (66) is neglected,that is when the equation stage 21a already operates before 11) 0. Thepercentage error which is made when ('i/r) 0 is assumed, is larger, thelarger the distance between pulses 1' It is shown here that it is veryadvantageous that in the circuit in accordance with this invention allvoltage values are related to the distance between pulses and notdirectly to the angular velocity. The start of operation of the firstthresholcl circuit 21a is advanced relative to the time in which (1) isequal to zero by a percentage of the distance between pulses 1' whichincreases the larger this distance between pulses. The time constant ofthe system is larger the larger the distance between pulses 'r that isthe smaller the angular velocity. The above-mentioned approximationcompensates for the time constants of the circuits, since for large Tthe initiation of the operation of the threshold switch is advancedfurther. One can thus achieve an advance in the initiation of theoperation of first comparator stage 21a which is almost independent ofthe angular wheel velocity, thereby compensating almost completely forthe already small delay time introduced by the control circuit.

Thus the regulating process does not follow along the same lines in thesecond embodiment as in the first em bodiment. The pressure decreasingvalve is opened when the wheel deceleration exceeds an upper limitingvalue, and is closed shortly beofre the seocnd derivative of velocitywith respect to time, (I) is equal to zero. It is thus possible toachieve the operating point A of FIG. 7, independent of the conditionsof the road. Just this type of operation, independent of roadconditions, could be achieved by known control circuits for preventingthe locking of the wheels of a vehicle only with extremely great amountsof electronic equipment.

Thus the control arrangement described above fulfills first therequirement for a substantial decrease in the delay time without anincrease in electronic components. Further, it also, in the secondembodiment allows operation independent of the road conditions. Thisoperation requires only a single additional differentiation circuit,namely circuit 27.

The circuit of the second embodiment of the present invention may befurther simplified as shown in FIG. 3b, where the second differentiatingcircuit 27 is omitted. The output voltage of the inverter 20 is appliedto both inputs of operational amplifier 210a. Capacitor 218 effects aphase shift between the two input voltages 60 and 61 (see FIG. 9). Whenthe function f/r reaches a maximum, a change in the sign of thedifference between the two input voltages 60 and 61 occurs, so that theoutput voltage of operational amplifier 210 changes sign. Curve 62 showsthe corresponding variation of output voltage of operational amplifier210a with respect to time.

The circuit of FIG. 3b has the further advantage that a change in signof the difference of the two input voltages, 60, 61, occurs even when awheel locks completely and suddenly, so that in any case the pressuredecreasing valve is again closed.

A further difficulty is present in all known arrangements for preventingthe locking of wheels of vehicles. This is that these circuits areparticularly sensitive to stray noise pulses. Such noise pulses cancause oscillations in the circuits, so that the pressure decreasingvalve 25 may be opened and closed at a relatively high frequency of 40to 50 Hz for no visible reason. In theory it is possible that suchoscillations may be suppressed by a low pass filter which is arrangedbetween the storage stage 23 and amplifier 24. However, such a low passfilter generates an additional delay time which is of course to beavoided. Thus it has been found advantageous to insert a digital lowpass filter as shown in FIG. 4.

The normal regulating frequency of the control circuit is approximately6 Hz. A maximum frequency of 20 Hz is still admissible. Thus one designsthe third monostable stage 30 for a pulse width of approximately 50milliseconds. If the storage 23 yields a positive output pulse and thusopens valve 25 via line 44, a pulse of the third monostable stage 30starts simultaneously. The output voltage of third comparator stage 32is generally negative, since the line 44 is connected to the invertinginput of operational amplifier 320. It may however become positive if apositive voltage is supplied to the direct input of operationalamplifier 320 by the third monostable stage 30 and when simultaneouslythe input voltage to the inverting input of operational amplifier 320 isnegative. This is the case when the output pulse from stage 23 stopsbefore the output pulse from stage 30 has stopped. Such behaviour is,however, a sign of an unwanted oscillation in the control circuitry.

As soon as the output of the third comparator stage 32 is positive, thefourth monostable stage 33 is switched to its unstable state whereinpower transistor 240 is blocked via switching transistor 350. Thepressure decreasing valve 25 remains closed until such time as the pulsefrom the fourth monostable stage has ended, that is a time ofapproximately 50 milliseconds. During a time of 50 milliseconds unwantedoscillations in the circuit have generally died down.

Finally, a safety arrangement for storage 23 must still be discussed. Inaccordance with FIGS. 1 and 2 this stage is a monostable multivibrator.The pulse width of this monostable multivibrator is approximately 200milliseconds, so that the pressure decreasing valve 25 is, in any case,reclosed after 200 milliseconds, even if no acceleration signal isderived from the wheel. Thus the vehicle, upon failure of the pulsegenerator or the sawtooth generator, does not continue in an unbrakedfashion after the pressure decreasing valve has once been opened.However, in accordance with FIG. 4,

stage 23 is a bistable stage whose output is coupled back to its outputthrough a second monostable stage 28. This results in the same desirabletype of operation, while further permitting the reset time to be madeadjustable in experimental circuits.

Thus in addition to the above-mentioned advantages, the circuits of thepresent invention offer safe operation in case of malfunctioning ofparts of the control circuit and suppression of unwanted oscillations ofthe control circuit. All these advantages can be incorporated into knowncontrol circuits of this type only with substantially greater amounts ofequipment.

While the invention has been illustrated and described as embodied in aspecific electronic circuit, it is not intended to be limited to thedetails shown, since various modifications and circuits and structuralchanges may be made without departing in any way from the spirit of thepresent invention.

Withour further analysis, the foregoing will so fully reveal the gist ofthe present invention that others can by applying current knowledgereadily adapt it for various applications without omitting featuresthat, from the standpoint of prior art, fairly constitute essentialcharacteristics of the generic or specific aspects of this inventionand, therefore, such adaptations should and are intended to becomprehended within the meaning and range of equivalence of thefollowing claims.

What is claimed as new and desired to be protected by Letters Patent isset forth in the appended claims:

1. In a motor vehicle having an internal combustion engine, anarrangement furnishing an acceleration signal for use as a control forthe brakes comprising, in combination, first circuit means coupled tosaid engine and responsive to the speed thereof, for furnishing a firstsignal having a first signal amplitude decreasing with increasing enginespeed; second circuit means connected to said first circuit means forreceiving said first signal and furnishing a second signal having asecond signal amplitude varying as a logarithmic function of said firstsignal amplitude; and differentiation circuit means connected to saidsecond circuit means differentiating said second signal, saidso-differentiated second signal constituting said acceleration signal.

2. An arrangement as set forth in claim 1, further comprising brakecontrol means operatively associated with the brakes of said motorvehicle; and first comparator means interconnected between saiddifferentiation means and said brake control means for operating saidbrake control means in dependence on said acceleration signal.

3. An arrangement as set forth in claim 2, wherein said first circuitmeans comprise pulse generator means coupled to a wheel of said motorvehicle for furnishing a pulse sequence having a pulse repetition ratepropor tional to the speed of said engine; and converter meansfurnishing a D.C. voltage having an amplitude decreasing with increasingpulse repetition rates, said D.C. voltage constituting said firstsignal.

4. An arrangement as set forth in claim 2, wherein said brake controlmeans comprise valve means decreasing the pressure in a brake uponreceipt of a brake control signal; and wherein said first comparatormeans furnish said brake control signal in dependence upon the amplitudeof said acceleration signal.

5. An arrangement as set forth in claim 4, wherein said first comparatormeans comprise additional differentiation means furnishing a secondderivative signal 13 corresponding to the second derivative with respectto time of the speed of said internal combustion engine. 6. Anarrangement as set forth in claim 3, wherein said converter meanscomprise sawtooth generator means; and peak rectifier means connected inseries with said sawtooth generator means.

7. An arrangement as set forth in claim 6, further comprising monostablecircuit means connected between said pulse generator means and saidsawtooth generator. means, for furnishing a sequence of rectangularpulses having a constant pulse width independent of said pulserepetition rate.

8. An arrangement as set forth in claim 7, wherein said sawtoothgenerator means comprise first storage capacitor means, first constantcurrent source means charging said first storage capacitor means in theintervals between said rectangular pulses, and discharge meansdischarging said first storage capacitor means for the duration of eachof said rectangular pulses.

9. An arrangement as set forth in claim 8, wherein said discharge meanscomprise first switching transistor means.

10. An arrangement as set forth in claim 9, wherein said first constantcurrent source means furnishes a current having an amplitudesubstantially less than the current flowing during the discharge of saidfirst storage capacitor means.

11. An arrangement as set forth in claim 6, wherein said peak rectifiermeans comprise first diode means, storage capacitor means connected inseries with said first diode means, and constant current source meansconnected to said storage capacitor means for effecting the dischargethereof.

12. An arrangement as set forth in claim 11, further comprisingdecoupling means interconnected between said first diode means and saidsawtooth generator means.

13. An arrangement as set forth in claim 12, wherein said decouplingmeans comprise an emitter-follower connected transistor stage.

14. An arrangement as set forth in claim 1, further comprising bandpassamplifier means connected between said second circuit means and saiddifferentiation circuit means, said bandpass amplifier means amplifyingsignals in a determined frequency range and suppressing frequenciesoutside of said determined frequency range.

15. An arrangement as set forth in claim 14, wherein said second circuitmeans comprise diode means furnishing a voltage varying as a logarithmicfunction of the current flowing therethrough.

16. An arrangement as set forth in claim 2, wherein said comparatormeans comprise a first and second comparator stage, having a first andsecond comparator output respectively; and first storage means connectedto said first and second comparator output.

17. An arrangement as set forth in claim 16, wherein said first andsecond comparator stage each have a first and second comparator input;further comprising means connecting said second inputs directly to theoutput of said first circuit means; inverter means connecting said firstinput of said first ocmparator stage to the output of said.differentiation circuit means; and means connecting said second input ofsaid second comparator stage directly to the output of saiddifferentiation circuit means.

18. An arrangement as set forth in claim 16, wherein said first andsecond comparator stages each comprise a first and second comparatorinput; further comprising inverter means connected to the output of saiddifferentiation circuit means; additional differentiation means havingan input connected to the output of said inverter means and an outputconnected to said first input of said first comparator stage; meansconnecting said second input of said first comparator stage directly toground potential; means connecting said first input of said secondcomparator stage directly to said output of said differentiation circuitmeans; and means connecting said second input of said second comparatorstage directly to the output of said first circuit means.

19. An arrangement as set forth in claim 16, wherein said first storagemeans comprise a first and second storage input respectively connectedto said first and second comparator outputs; wherein said brake controlmeans comprise electrically operated valve means; further comprisingswitching amplifier means connected between said first storage means andsaid electrically operative valve means. 7

20. An arrangement as set forth in claim 19, wherein said first storagemeans comprises monostable circuit means.

21. An arrangement as set forth in claim 19, wherein said first storagemeans comprise bistable circuit means having a bistable circuit output;further comprising monostable feedback circuit means connected from saidbistable circuit output to said second storage input.

22. An arrangement as set forth in claim 19, further comprising low passfilter means interconnected between said first storage means and saidswitching amplifier means.

23. An arrangement as set forth in claim 22, wherein said low passfilter means comprise digital low pass filter means.

24. An arrangement as set forth in claim 22, wherein said low passfilter means comprise switching transistor means connected to the inputof said switching amplifier means for short circuiting said input whenthe repetition rate of pulses at the output of said first storage meansexceeds a predetermined repetition rate.

25. An arrangement as set forth in claim 24, wherein said low passfilter means comprise comparator means having a first and secondcomparator input and an output; monostable circuit means connecting saidsecond comparator input to said output of said first storage means;means directly connecting said first comparator input of said comparatormeans to said output of said first storage means; wherein said switchingtransistor means has a base; and means connecting said output of saidcomparator means to said base of said switching transistor means.

26. An arrangement as set forth in claim 25, wherein said meansconnecting said output of said comparator means to the base of saidswitching transistor means comprise monostable circuit means.

27. An arrangement as set forth in claim 2, wherein said first circuitmeans comprise sample-and-hold circuit means.

* t t i

1. In a motor vehicle having an internal combustion engine, anarrangement furnishing an acceleration signal for use as a control forthe brakes comprising, in combination, first circuit means coupled tosaid engine and responsive to the speed thereof, for furnishing a firstsignal having a first signal amplitude decreasing with increasing enginespeed; second circuit means connected to said first circuit means forreceiving said first signal and furnishing a second signal having asecond signal amplitude varying as a logarithmic function of said firstsignal amplitude; and differentiation circuit means connected to saidsecond circuit means differentiating said second signal, saidsodifferentiated second signal constituting said acceleration signal. 2.An arrangement as set forth in claim 1, further comprising brake controlmeans operatively associated with the brakes of said motor vehicle; andfirst comparator means interconnected between said differentiation meansand said brake control means for operating said brake control means independence on said acceleration signal.
 3. An arrangement as set forthin claim 2, wherein said first circuit means comprise pulse generatormeans coupled to a wheel of said motor vehicle for furnishing a pulsesequence having a pulse repetition rate proportional to the speed ofsaid engine; and converter means furnishing a D.C. voltage having anamplitude decreasing with increasing pulse repetition rates, said D.C.voltage constituting said first signal.
 4. An arrangement as set forthin claim 2, wherein said brake control means comprise valve meansdecreasing the pressure in a brake upon receipt of a brake controlsignal; and wherein said first comparator means furnish said brakecontrol signal in dependence upon the amplitude of said accelerationsignal.
 5. An arrangement as set forth in claim 4, wherein said firstcomparator means comprise additional differentiation means furnishing asecond derivative signal corresponding to the second derivative withrespect to time of the speed of said internal combustion engine.
 6. Anarrangement as set forth in claim 3, wherein said converter meanscomprise sawtooth generator means; and peak rectifier means connected inseries with said sawtooth generator means.
 7. An arrangement as setforth in claim 6, further comprising monostable circuit means connectedbetween said pulse generator means and said sawtooth generator means,for furnishing a sequence of rectangular pulses having a constant pulsewidth independent of said pulse repetition rate.
 8. An arrangement asset forth in claim 7, wherein said sawtooth generator means comprisefirst storage capacitor means, first constant current source meanscharging said first storage capacitor means in the intervals betweensaid rectangular pulses, and discharge means discharging said firststorage capacitor means for the duration of each of said rectangularpulses.
 9. An arrangement as set forth in claim 8, wherein saiddischarge means comprise first switching transistor means.
 10. Anarrangement as set forth in claim 9, wherein said first constant currentsource means furnishes a current having an amplitude substantially lessthan the current flowing during the discharge of said first storagecapacitor means.
 11. An arrangement as set forth in claim 6, whereinsaid peak rectifier means comprise first diode means, storage capacitormeans connected in series with said first diode means, and constantcurrent source means connected to said storage capacitor means foreffecting the discharge thereof.
 12. An arrangement as set forth inclaim 11, further comprising decoupling means interconnected betweensaid first diode means and said sawtooth generator means.
 13. Anarrangement as set forth in claim 12, wherein said decoupling meanscomprise an emitter-follower connected transistor stage.
 14. Anarrangement as set forth in claim 1, further comprising bandpassamplifier means connected between said second circuit means and saiddifferentiation circuit means, said bandpass amplifier means amplifyingsignals in a determined frequency range and suppressing frequenciesoutside of said determined frequency range.
 15. An arrangement as setforth in claim 14, wherein said second circuit means comprise diodemeans furnishing a voltage varying as a logarithmic function of thecurrent flowing therethrough.
 16. An arrangement as set forth in claim2, wherein said comparator means comprise a first and second comparatorstage, having a first and second comparator output respectively; andfirst storage means connected to said first and second comparatoroutput.
 17. An arrangement as set forth in claim 16, wherein said firstand second comparator stage each have a first and second comparatorinput; further comprising means connecting said second inputs directlyto the output of said first circuit means; inverter means connectingsaid first input of said first comparator stage to the output of saiddifferentiation circuit means; and means connecting said second input ofsaid second comparator stage directly to the output of saiddifferentiation circuit means.
 18. An arrangement as set forth in claim16, wherein said first and second comparator stages each comprise afirst and second comparator input; further comprising inverter meansconnected to the output of said differentiation circuit means;additional differentiation means having an input connected to the outputof said inverter means and an output connected to said first input ofsaid first comparator stage; means connecting said second input of saidfirst comparator stage directly to ground potential; means connectingsaid first input of said second comparator stage directly to said outputof said differentiation circuit means; and means connecting said secondinput of said second comparator stage directly to the output of saidfirst circuit means.
 19. An arrangement as set forth in claim 16,wherein said first storage means comprise a first and second storageinput respectively connected to said first and second comparatoroutputs; wherein said brake control means comprise electrically operatedvalve means; further comprising switching amplifier means connectedbetween said first storage means and said electrically operative valvemeans.
 20. An arrangement as set forth in claim 19, wherein said firststorage means comprises monostable circuit means.
 21. An arrangement asset forth in claim 19, wherein said first storage means comprisebistable circuit means having a bistable circuit output; furthercomprising monostable feedback circuit means connected from saidbistable circuit output to said second storage input.
 22. An arrangementas set forth in claim 19, further comprising low pass filter meansinterconnected between said first storage means and said switchingamplifier means.
 23. An arrangement as set forth in claim 22, whereinsaid low pass filter means comprise digital low pass filter means. 24.An arrangement as set forth in claim 22, wherein said low pass filtermeans comprise switching transistor means connected to the input of saidswitching amplifier means for short circuiting said input when therepetition rate of pulses at the output of said first storage meansexceeds a predetermined repetition rate.
 25. An arrangement as set forthin claim 24, wherein said low pass filter means comprise comparatormeans having a first and second comparator input and an output;monostable circuit means connecting said second comparator input to saidoutput of said first storage means; means directly connecting said firstcomparator input of said comparator means to said output of said firststorage means; wherein said switching transistor means has a base; andmeans connecting said output of said comparator means to said base ofsaid switching transistor means.
 26. An arrangement as set forth inclaim 25, wherein said means connecting said output of said comparatormeans to the base of said switching transistor means comprise monostablecircuit means.
 27. An arrangement as set forth in claim 2, wherein saidfirst circuit means comprise sample-and-hold circuit means.